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CXD3508TQ
LCD Interface IC For the availability of this product, please contact the sales office.
Description The CXD3508TQ is a LCD interface IC for the color LCD module ACX704AKM driver. Features * Generates the color LCD module ACX704AKM drive pulse. * Standby mode function * Thin package (100-pin TQFP) Applications PDA, compact LCD monitor, etc. Structure Silicon gate CMOS IC Absolute Maximum Ratings (Ta = 25C) * Supply voltage VDD Vss - 0.3 to +5.5 * Input voltage VI Vss - 0.3 to VDD + 0.3 * Output voltage VO Vss - 0.3 to VDD + 0.3 * Operating temperature Topr -25 to +75 * Storage temperature Tstg -55 to +150 Recommended Operating Conditions * Supply voltage VDD 3.0 to 3.6 * Operating temperature Topr -10 to +60 100 pin TQFP (Plastic)
V V V C C
V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E00228-PS
CXD3508TQ
Block Diagram
R0 R1 R2 R3
9 8 7 6 31 to 28 R01, R11, R21, R31 43 to 41 XR01, XR11, XR21, XR31 94 to 97 R02, R12, R22, R32 82 to 89 XR02, XR12, XR22, XR32 35 to 32 G01, G11, G21, G31 Serial/ Parallel Conversion Block 47 to 44 XG01, XG11, XG21, XG31 90 to 93 G02, G12, G22, G32 78 to 81 XG02, XG12, XG22, XG32 39 to 36 B01, B11, B21, B31 53, 52, 49, 48 XB01, XB11, XB21, XB31
G0 13 DATA IN G1 12 G2 11 G3 10 B0 17 B1 16 B2 15 B3 14 FA 24 MCK 20
86 to 89 B02, B12, B22, B32 72 to 74, XB02, XB12, XB22, XB32 77
PCI 21
Power CTR.
27 PCO
Hsync/DENB 18 SLIN 22
H Counter Delay
64 HST1 65 XHST1 66 HST2 67 XHST2 60 HCK1
H Timing Pulse GEN.
Delay
61 XHCK1 62 HCK2 63 XHCK2 68 OE1 69 XOE1 70 OE2 71 XOE2 54 VST 55 XVST
V sync 19
V Counter
V Timing Pulse GEN.
58 VCK 59 XVCK 56 ENB 57 XENB 98 FRP
Timing Generator Block
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CXD3508TQ
Pin Configuration
XHCK2 XHCK1 XHST2 XHST1
XVCK
XOE1
XOE2
HCK2
HCK1
XENB
HST2
HST1
XVST
XB22
XB12
XB02
XB01
OE2
OE1
VSS
XB11
VCK
ENB
VST
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VDD 76 XB32 77 XG02 78 XG12 79 XG22 80 XG32 81 XR02 82 XR12 83 XR22 84 XR32 85 B02 86 B12 87 B22 88 B32 89 G02 90 G12 91 G22 92 G32 93 R02 94 R12 95 R22 96 R32 97 FRP 98 TESTV 99 VDD 100
VSS 50 VDD 49 XB21 48 XB31 47 XG01 46 XG11 45 XG21 44 XG31 43 XR01 42 XR11 41 XR21 40 XR31 39 B01 38 B11 37 B21 36 B31 35 G01 34 G11 33 G21 32 G31 31 R01 30 R11 29 R21 28 R31 27 PCO 26 VDD VSS
1 VSS
2 TEST1
3 TEST2
4 VSS
5 CLR
6 R3
7 R2
8 R1
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Hsync/DENB Vsync MCK PCI R0 G3 G2 G1 G0 B3 B2 B1 B0 TESTP SLIN FA
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CXD3508TQ
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Symbol VSS TEST1 TEST2 VSS CLR R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 Hsync/DENB Vsync MCK PCI SLIN TESTP FA VSS VDD PCO R31 R21 R11 R01 G31 G21 I/O -- I I -- I I I I I I I I I I I I I I I I I I I I -- -- O O O O O O O GND Test signal input Test signal input GND System reset Red signal input (MSB) Red signal input Red signal input Red signal input (LSB) Green signal input (MSB) Green signal input Green signal input Green signal input (LSB) Blue signal input (MSB) Blue signal input Blue signal input Blue signal input (LSB) Hsync/data enable pulse input Vsync pulse input Dot clock input Power control signal input Sync input signal mode switch Test signal input Data phase adjustment GND Power supply Power control signal output Red signal output Red signal output Red signal output Red signal output Green signal output Green signal output Description Input pin for open status -- DWN1 DWN1 -- UP2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DWN1 DWN1 DWN1 -- -- -- -- -- -- -- -- --
1 Built-in pull-down resistor (82.5k) 2 Built-in pull-up resistor (82.5k) -4-
CXD3508TQ
Pin No. 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67
Symbol G11 G01 B31 B21 B11 B01 XR31 XR21 XR11 XR01 XG31 XG21 XG11 XG01 XB31 XB21 VDD VSS XB11 XB01 VST XVST ENB XENB VCK XVCK HCK1 XHCK1 HCK2 XHCK2 HST1 XHST1 HST2 XHST2
I/O O O O O O O O O O O O O O O O O -- -- O O O O O O O O O O O O O O O O Green signal output Green signal output Blue signal output Blue signal output Blue signal output Blue signal output
Description
Input pin for open status -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Red signal output (inverse) Red signal output (inverse) Red signal output (inverse) Red signal output (inverse) Green signal output (inverse) Green signal output (inverse) Green signal output (inverse) Green signal output (inverse) Blue signal output (inverse) Blue signal output (inverse) Power supply GND Blue signal output (inverse) Blue signal output (inverse) VST pulse output VST pulse output (inverse) ENB pulse output ENB pulse output (inverse) VCK pulse output VCK pulse output (inverse) HCK1 pulse output HCK1 pulse output (inverse) HCK2 pulse output HCK2 pulse output (inverse) HST1 pulse output HST1 pulse output (inverse) HST2 pulse output HST2 pulse output (inverse)
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CXD3508TQ
Pin No. 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Symbol OE1 XOE1 OE2 XOE2 XB02 XB12 XB22 VSS VDD XB32 XG02 XG12 XG22 XG32 XR02 XR12 XR22 XR32 B02 B12 B22 B32 G02 G12 G22 G32 R02 R12 R22 R32 FRP TESTV VDD
I/O O O O O O O O -- -- O O O O O O O O O O O O O O O O O O O O O O I -- OE1 pulse output
Description
Input pin for open status -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DWN1 --
OE1 pulse output (inverse) OE2 pulse output OE2 pulse output (inverse) Blue signal output (inverse) Blue signal output (inverse) Blue signal output (inverse) GND Power supply Blue signal output (inverse) Green signal output (inverse) Green signal output (inverse) Green signal output (inverse) Green signal output (inverse) Red signal output (inverse) Red signal output (inverse) Red signal output (inverse) Red signal output (inverse) Blue signal output Blue signal output Blue signal output Blue signal output Green signal output Green signal output Green signal output Green signal output Red signal output Red signal output Red signal output Red signal output Polarity inversion pulse signal output Test signal input Power supply
1 Built-in pull-down resistor (82.5k)
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CXD3508TQ
Electrical Characteristics DC Characteristics Item Supply voltage Current consumption Input voltage 1 Symbol VDD IDD VIH1 VIL1 Vt+ Input voltage 2 Vt- Vt+ - Vt- | IIL1 | Input current 1 | IIH1 | Input current 2 | IIL2 | | IIH2 | | IIL3 | Input current 3 | IIH3 | Output voltage 1 VOL1 VOH1 R0, R1, R2, R3, G0, G1, G2, G3, B0, B1, B2, B3, Hsync/DENB, Vsync, MCK, PCI CLR TEST1, TEST2, SLIN, TESTV, FA, TESTP ENB, XENB IOH1 = -0.50mA VDD - 0.2 R01, R11, R21, R31, R02, R12, R22, R32, XR01, XR11, XR21, XR31, XR02, XR12, XR22, XR32, G01, G11, G21, G31, G02, G12, G22, G32, XG01, XG11, XG21, XG31, XG02, XG12, XG22, XG32, B01, B11, B21, B31, B02, B12, B22, B32, XB01, XB11, XB21, XB31, XB02, XB12, XB22, XB32, PCO, VST, XVST, VCK, XVCK, OE1, XOE1, OE2, XOE2, FRP HST1, XHST1, HST2, XHST2 HCK1, XHCK1, HCK2, XHCK2 All output pins excluding MCK VDD -- Applicable pins Conditions -- No load, Ta = 25C, VDD = 3.3V, MCK: 5.58MHz LVTTL input cell LVTTL Schmitt trigger input cell VI = 0V VI = VDD VI = 0V VI = VDD VI = 0V VI = VDD IOL1 = 0.75mA 10 10 2.0 0.8 2.0 0.5 0.2 1.0 A 1.0 100 3.0 3.0 A 100 0.2 V A V (VDD = 3.0 to 3.6V, Ta = -25 to + 75C) Min. 3.0 Typ. 3.3 0.9 Max. 3.6 Unit V mA
MCK
V
VOL2
IOL2 = 1.5mA
0.2
Output voltage 2
V
VOH2
IOH2 = -1.0mA VDD - 0.2
Output voltage 3 Output voltage 4
VOL3 VOH3 VOL4 VOH4
IOL3 = 3.0mA IOH3 = -2.0mA VDD - 0.2 IOL4 = 4.5mA IOH4 = -3.0mA VDD - 0.2
0.2
V
0.2 V
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CXD3508TQ
AC Characteristics Item HCK, HST time difference Symbol tHST-HCKU tHST-HCKD Applicable pins HCK1, HCK2, XCHK1, XHCK2, HST1, HST2, XHST1, XHST2 R01, R11, R21, R31, R02, R12, R22, R32, XR01, XR11, XR21, XR31, XR02, XR12, XR22, XR32, G01, G11, G21, G31, G02, G12, G22, G32, XG01, XG11, XG21, XG31, XG02, XG12, XG22, XG32, B01, B11, B21, B31, B02, B12, B22, B32, XB01, XB11, XB21, XB31, XB02, XB12, XB22, XB32 HCK1, HCK2, XCHK1, XHCK2, HST1, HST2, XHST1, XHST2 VCK, XVCK, VST, XVST, OE1, OE2, XOE1, XOE2, FRP, PCO GND - VDD (0 - 90%) Conditions
(VDD = 3.0 to 3.6V, Ta = -10 to +60C) Min. Typ. Max. 152 Unit ns
Data output rise time
tRD
40 ns
Data output fall time
tFD
VDD - GND (100 - 10%)
40
H pulse output rise time H pulse output fall time V pulse output rise time V pulse output fall time ENB pulse output rise time ENB pulse output fall time
tRHP tFHP tRVP tFVP tREP
GND - VDD (0 - 90%) VDD - GND (100 - 10%) GND - VDD (0 - 90%) VDD - GND (100 - 10%) GND - VDD (0 - 90%) VDD - GND (100 - 10%)
30 ns 30 60 ns 60 80 ns 80
ENB, XENB
tFEP
HCK1, HCK2, XHCK1, XHCK2, DATA setup time
tSTP
HCK1, HCK2, XHCK1, XHCK2, R01, R11, R21, R31, R02, R12, R22, R32, XR01, XR11, XR21, XR31, XR02, XR12, XR22, XR32, G01, G11, G21, G31, G02, 3 G12, G22, G32, XG01, XG11, XG21, XG31, XG02, XG12, XG22, XG32, B01, B11, B21, B31, B02, B12, B22, B32, XB01, XB11, XB21, XB31, XB02, XB12, XB22, XB32 HCK1, HCK2, XHCK1, XHCK2, VCK, XVCK 4
35
50
120
ns
HCK, VCK duty
dHCK dVCK
48
50
52
%
1 CL of each output pin is shown below. * R01, R11, R21, R31, R02, R12, R22, R32, XR01, XR11, XR21, XR31, XR02, XR12, XR22, XR32, G01, G11, G21, G31, G02, G12, G22, G32, XG01, XG11, XG21, XG31, XG02, XG12, XG22, XG32, B01, B11, B21, B31, B02, B12, B22, B32, XB01, XB11, XB21, XB31, XB02, XB12, XB22, XB32, ENB, XENB: CL = 70pF * HCK1, HCK2, XHCK1, XHCK2 : CL = 150pF * HST, XHST, VCK, XVCK : CL = 100pF * VST, XVST : CL = 85pF * OE1, XOE1, OE2, XOE2, PCO, FRP : CL = 60pF 2 The absolute value of time difference (HST1, XHST1, HCK1, XHCK1) is within 15ns. In the same manner, the absolute value of time difference (HST2, XHST2, HCK2, XHCK2) is within 15ns. 3 tSTP: tST1D, tST1U, tST2D, tST2U 4 dHCK = (tHH/(tHH + tHL)) x 100, dVCK = (tVH/(tVH + tVL)) x 100 -8-
CXD3508TQ
Timing Definition H system
tHH
tHL VDD
HCK1
50%
50%
50% GND VDD
XHCK1
50% GND tH tH
VDD HCK2 50% 50% 50% GND VDD XHCK2 50% 50% GND tH tH
VDD HST1 (HST2) 50% 50% GND VDD XHST1 (XHST2) 50% 50% GND VDD HCK1 (HCK2) 50% 50% GND VDD XHCK1 (XHCK2) 50% 50% GND tHST-HCKU tHST-HCKD
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CXD3508TQ
V system
tVH
tVL VDD
VCK
50%
50%
50% GND VDD
XVCK
50%
50% GND
tV
tV
DATA
VDD HCK1 50% 50% GND VDD XHCK1 50% 50% GND
VDD HCK2 50% 50% GND VDD XHCK2 50% GND
VDD DATA GND tST1D tST2D tST1U tST2U
tSTX1U
tSTX2U
tSTX1D
tSTX2D
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CXD3508TQ
PCI, PCO These pins control to turn power on/off of the ACX704AKM and the CXD2475TQ when the LCD is turned on/off. Connect PCO to DC-DC converter that can control power on/off of the ACX704AKM and the CXD2475TQ. * When LCD is on, effective screen is displayed after entire white display (2 fields). * When LCD is off, LCD is off after entire white display.
Power Up Sequence
VDD 0 VDD CLR PCI PCO Pulse DATA (out) MCK Hsync Vsync DENB DATA (in) Inactive (low) Inactive (low) Inactive (low) Inactive (low) 0 Active Active
VDD
Active White Data 2 Fields Valid
Invalid (low)
Valid
1 Field (typ.) 288H (min.)
Power Down Sequence (Standby)
Standby Mode PCI PCO VDD DATA Pulse Valid White Data Invalid (all low) Active (high) Active (high) Inactive (low) Inactive (low) VDD 0
Valid
Invalid (all low)
Vsync DENB 3 Fields 10 Fields
HST1, HST2, XHST1, XHST2, HCK1, HCK2, XHCK1, XHCK2, VST, XVST, VCK, XVCK, ENB. XENB, OE1, XOE1, OE2, XOE2, FRP
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CXD3508TQ
FA This is a selector switch for phase relationship between data and other pulses. (Normally, set to low.)
MCK
HCK1 XHCK1 HCK2 XHCK2
(FA: L) Default
OUTPUT DATA R/G/B 01 to 31 OUTPUT DATA R/G/B 02 to 31
Invalid Invalid
2 1
4 3
6 5
8 7
(FA: H)
OUTPUT DATA R/G/B 01 to 31 OUTPUT DATA R/G/B 02 to 31
Invalid Invalid
2 1
4 3
6 5
8 7
SLIN This is a selector switch for input sync signal mode. SLIN: LOW Hsync + Vsync Mode SLIN: HIGH DENB ONLY Mode (Vsync input is invalid.)
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Horizontal Direction Input Signal Timing Chart
352 dots 320 325 330 335 340 345 350 0 5
310
315
MCK
Hsync 16 dots 4 dots (min.) 16 dots
DENB 32 dots
1 2 3 4 5 6 7 8 9 10 11
DATA
307 308 309 310 311 312 313 314 315 316 317 318 319 320
tch
tcl
MCK tclk tdes tdeh
Hsync
thss
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1 tds tdh 2 320
DENB
thsw
DATA
Input either Hsync + Vsync or DENB as sync signal input.
Input Signal AC Characteristics (VDD = 3.0 to 3.6V, Ta = -25 to +75C) Item MCK frequency MCK low, high pulse width DATA setup time DATA hold time DENB setup time DENB hold time Hsync setup time Hsync low pulse width Symbol ftch Min. 3MHz Typ. 5.58MHz 0.5tclk 10ns 15ns 10ns 15ns 10ns 4tclk 16tclk
CXD3508TQ
Max. 8MHz
tch, tcl tds tdh tdes tdeh thss thsw
Vertical Direction Input Signal Timing Chart
264 lines 240 245 250 255 260 0 5 10 15
230
235
Hsync
Vsync 10 lines 14 lines
DENB
Hsync
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tvsw
tvhde
Vsync
DENB
DATA
Input either Hsync + Vsync or DENB as sync signal input.
Input Signal AC Characteristics (VDD = 3.0 to 3.6V, Ta = -25 to +75C) Item Vsync falling edge Hsync rising edge Vsync low pulse width Symbol Min. Typ. Max.
tvhde tvsw
334tclk 2 lines
349tclk 14 lines
CXD3508TQ
Horizontal Direction Timing Chart
290 300 310 320 330 340 0 10 20 352 dot
280
MCK 16 dot 16 dot 32 dot
123456789
316 317 318 319 320
Hsync
DENB
Input
DATA
Output
270 272 274 276 278 280 282 284 286 288 290 292 294 296 298 300 302 304 306 308 310 312 314 316 318 320 1 3 5 7 9
2
4
6
8
10 12 14 16 18 20 22 24 11 13 15 17 19 21 23
R/G/B 01 to 31 R/G/B 02 to 32 344 4 dot 348
269 271 273 275 277 279 281 283 285 287 289 291 293 295 297 299 301 303 305 307 309 311 313 315 317 319
HST1
XHST1
HCK1
XHCK1 342 4 dot 346
HST2
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328 340 320 304 334 334 334
XHST2
HCK2
XHCK2
OE1
XOE1 0
OE2
XOE2 0
ENB 350
XENB
VST
XVST
VCK
XVCK
CXD3508TQ
FRP
Vertical Direction Timing Chart
264 lines 245 250 255 260 0 5 10 15 20
240
Hsync 14 line
Vsync
10 line
Input
DENB
Output
VST
XVST
VCK
XVCK
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ENB
XENB
OE1
XOE1
OE2
XOE2
FRP (O)
FRP (E)
FRP (O): FRP output timing at odd field.
CXD3508TQ
FRP (E): FRP output timing at even field.
CXD3508TQ
Application Circuit
To ACX704AKM VDD
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 XVCK VCK XENB ENB XVST XB22 XB12 XB02 XOE2 OE2 XOE1 OE1 XHST2 HST2 XHST1 HST1 XHCK2 HCK2 XHCK1 HCK1 VST XB01 XB11 VSS VSS VDD 50 XB21 49 XB31 48 XG01 47 XG11 46 XG21 45 XG31 44 XR01 43 XR11 42 XR21 41 XR31 40 B01 39 B11 38 B21 37 B31 36 G01 35 G11 34 G21 33 G31 32 R01 31 R11 30 R21 29 R31 28 Hsync/DENB PCO 27 TESTP VDD 26 VSS FA Vsync SLIN MCK To ACX704AKM To DC-DC Converter To CXD2475TQ (Pins 9, 10) Input VDD
76 VDD 77 XB32 78 XG02 79 XG12 80 XG22 81 XG32 82 XR02 83 XR12 84 XR22 To ACX704AKM 85 XR32 86 B02 87 B12 88 B22 89 B32 90 G02 91 G12 92 G22 93 G32 94 R02 95 R12 96 R22 97 R32 98 FRP 99 TESTV TEST1 TEST2 100 VDD VSS
CLR
VSS
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VDD
Connect PCO to DC-DC converter that can control power on/off of the ACX704AKM and the CXD2475TQ.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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PCI
G3
G2
G1
G0
R3
R2
R1
R0
B3
B2
B1
B0
CXD3508TQ
Package Outline
Unit: mm
TQFP-100P-L111
1.2 MAX 16.0 0.3 14.0 0.2 75 51 0.4375 0.1 1.0 0.1
76
50
A 100 26
1 0.2 0.06 0.08 0.1 0.1 M
25 0.5
0.125
15.0 0.2
0.05
0 to 10 DETAIL A
SONY CODE EIAJ CODE JEDEC CODE TQFP-100P-L111 P-TQFP100-14X14-0.5
PACKAGE STRUCTURE
PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING 42ALLOY 0.6g
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Sony Corporation

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